VLSI Openings
PHYSICAL DESIGN
- PD Engineers 3 to 5 years and Lead with 5+ years of experience.
- Location: Bangalore – ODC project
- No. of positions: 6 Position’s
- The candidate is expected to have experience in working with physical design functions like chip level planning, synthesis, timing constraints, PnR, CTS, knowledge of all PD signoffs.
DV Design Verification
Hello We are looking for Design Verification Engineers Experience to join our team! EDIC Semicon
- 3+ years of experience in IP/SOC verification
- Strong expertise in DDR protocols
- Hands-on experience with verification methodologies (UVM, System Verilog.)
DFT(Design For Testability)
Experience : (2-5 Years Experience)
Location : Bengaluru
Exciting opportunity to work on advanced chip designs in Bengaluru
Experience in ATPG, Scan-Insertion, Simulation, BITS & MBIST required.
Proficiency in tools like SpyGlass, Verdi, Tessent Fastscan, and TestKompress essential.
BTech/MTech graduates (2019-2021)